The present invention relates to a method and/or architecture for transmission line impedance matching generally and, more particularly, to a method and/or architecture for programmable transmission line impedance matching.
In integrated circuits, such as microprocessors, memories, and the like, signals may be routed for relatively long distances using transmission lines. A transmission line may be a bus, a printed circuit board trace, or other type of relatively long metal line for transporting a digital signal. Typically, a printed circuit board trace has a characteristic impedance of between 50 and 75 ohms. The receiving end, or far end, of the transmission line can be connected to an input of a logic circuit, where the input impedance is higher than the characteristic impedance of the transmission line. If the impedance coupled to the far end of the transmission line is different than the impedance of the transmission line, the signal can be reflected back to the sending end, causing the signal to overshoot a desired steady state voltage for the logic state. The signal may be reflected back and forth many times between the near end of the transmission line and the far end of the transmission line. The reflected signal can cause oscillatory behavior of the signal at both ends of the transmission line. The repeated overshooting and undershooting of the signal is commonly known as xe2x80x9cringingxe2x80x9d, and results in reduced noise immunity and increased time for the signal to become, and remain, valid at the far end.
Referring to FIG. 1, a diagram of a circuit 10 illustrating a complementary metal-oxide semiconductor (CMOS) output driver is shown. The circuit 10 is used to provide enough current to drive a signal the length of a transmission line 12. The CMOS driver circuit 10 includes a P-channel transistor 14 and an N-channel transistor 16 connected in series between a positive power supply voltage terminal VCC and a ground terminal VSS. The gates of the transistors receive an input signal IN, and an output terminal of the driver circuit is located between the transistors. The P-channel transistor 14 functions as a xe2x80x9cpull-upxe2x80x9d transistor, and the N-channel transistor 16 functions as a xe2x80x9cpull-downxe2x80x9d transistor. The output impedance of the driver circuit 10 is set by a series resistor 18. The resistor 18 has a resistance Rt that is selected to match the characteristic impedance of the transmission line 12. The impedance must be matched in order for the driver circuit to absorb the reflected signal and prevent ringing. Depending on the particular application in which the driver circuit 10 is installed, the load impedance that the driver circuit is required to drive can vary. The output circuit 10 has a disadvantage of requiring a separate discrete resistor for each output. The resistors must be changed for different transmission line impedances.
Referring to FIG. 2, a diagram of a circuit 20 illustrating a conventional buffer circuit having a variable output impedance is shown. The output buffer circuit 20 has an output impedance that is adjustable. An external resistor 32 having a resistance that is a multiple of the desired output impedance is coupled to the output buffer circuit 20. A voltage across the resistor 32 is converted to a digital codes using analog-to-digital (A/D) converters 22 and 24. A digital code from the A/D converters 22 and 24 are used to adjust a resistance of binary weighted transistor arrays 45 and 46 to match the resistance of the external resistor 32.
A plurality of binary weighted output transistors in the output driver are selected in response to the digital codes to adjust the output impedance of the output buffer circuit 20. The output impedance can be adjusted by changing the resistance of external resistor 32. A description of the circuit 20 may be found in U.S. Pat. No. 5,606,275, which is hereby incorporated by reference in its entirety. The circuit 20 has the disadvantages of (i) a single update algorithm that can have a slow settling time on power-up and (ii) abrupt impedance changes during updates due to the binary-weighted transistor arrays.
The present invention concerns an apparatus comprising a first circuit , a second circuit, and an output circuit. The first circuit may be configured to generate a first digital output in response to (i) a reference input and (ii) a feedback input. The second circuit may be configured to generate a second digital output in response to (i) the first digital output and (ii) a second feedback input. The output circuit may be configured to generate a third output in response to a data input, wherein an output impedance of the output circuit is adjusted in response to (i) the first digital output and (ii) the second digital output.
The objects, features and advantages of the present invention include providing a method and/or architecture for a programmable transmission line impedance matching circuit that may (i) match an impedance of one or more output drivers to an impedance of one or more transmission lines using a single discrete resistor, (ii) provide a test mode output impedance of 50 ohms, (iii) provide a minimum output impedance mode, (iv) provide separate control for pull-up and pull-down, (v) provide a controlled impedance over the entire switching range, (vi) use a binary search process to determine impedance on power-up, and/or (vii) use different processes for power-up and updates.